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MPC92469 idt? / ics? pecl clock synthesizer w/spread spectrum 1 MPC92469rev 4 january 23, 2007 400 mhz low voltage pecl clock synthesizer w/spread spectrum the MPC92469 is a 3.3 v compatible, pll based clock synthesizer targeted for high performance clock generation in mid-range to high-performance tele- com, networking and computing applicat ions. with output frequencies from 25 mhz to 400 mhz and the support of differential pecl output signals the device meets the needs of the most demanding clock applications. features ? 25 mhz to 400 mhz synthesized clock output signal ? differential pecl output ? lvcmos compatible control inputs ? on-chip crystal oscillator for reference frequency generation ? spread spectrum output for emi reduction ? 3.3 v power supply ? fully integrated pll ? minimal frequency overshoot ? serial 3-wire programming interface ? parallel programming interface for power-up ? 32-lead lqfp packaging ? 32-lead pb-free package available ? sige technology ? ambient temperature range 0 c to +70 c ? pin compatible to the mc12429, mpc9229, mpc92429, and ics84329 functional description the internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference. the frequency of the internal crystal oscillator is divided by 16 and then multiplie d by the pll. the vco within the pll operates over a range of 40 0 to 800 mhz. its output is scaled by a divi der that is configured by either the serial or parallel interfaces. the crystal oscil lator frequency f xtal , the pll feedback-divider m and the pll post -divider n determine the output frequency. the feedback path of the pll is internal. the pll adjusts the vco output frequency to be 2 ? m times the reference frequency by adjusting the vco control voltage. note that for some values of m (either too high or too low) the pll will not achieve phas e lock. the pll will be stable if the vco frequency is within the specified vco frequency range (400 to 800 mhz). the m-value must be programmed by the serial or parallel interface. the pll post-divider n is configured through either the serial or the parallel interfac es, and can provide one of four division ratios (1, 2, 4, or 8). this divider ext ends performance of the part wh ile providing a 50% duty cycle. the output driver is dri ven differentially from the output divider, and is capable of driving a pair of transmission lines terminated 50 ? to v cc ? 2.0 v. the positive supply voltage for the internal pll is separated from the power supply for the core logic and output drivers to minimi ze noise induced jitter. the configuration logic has two sections: serial and parallel. the parallel interface uses the valu es at the m[8:0] and n[1:0] inputs to configure the internal counters. it is recommended on system reset to hold the p_load input low until power becomes valid. on the low-to-high transition of p_load , the parallel inputs are captured. the para llel interface has priority over the serial interface. internal pullup resistors are provided on the m[8:0] and n[1:0] in puts prevent the lvcmos compatible control inputs from floating. the serial interface centers on a eighteen bit shift register. the shift register shifts once per rising edge of the s_clock in put. the serial input s_data must meet setup and hold timing as spec ified in the ac characteristics section of this document. the configuration latches will capture the value of the shift r egister on the high-to-low edge of the s_load input. see program- ming interface for more information. the test output reflects variou s internal node values, and is controlled by the t[2:0] bits in the serial data stream. in order to minimize the pll ji tter, it is recommended to avoid active signal on the test outpu t. 400 mhz low voltage clock synthesizer w/spread spectrum fa suffix 32-lead lqfp package case 873a-03 ac suffix 32-lead lqfp package pb-free package case 873a-03
package dimensions MPC92469 400mhz, low voltage, pecl cloc k synthesizer w/spread spectrum idt? / ics? pecl clock synthesizer w/spread spectrum 2 MPC92469rev 4 january 23, 2007 figure 1. MPC92469 logic diagram figure 2. MPC92469 32-lead package pinout (top view) 1 2 4 8 xtal_in xtal_out s_load 16 s_data s_clock m[0:8] xtal pll ref fb vco 400 ? 800 mhz 00 01 10 11 9-bit m-divider m-latch n-latch 12 ? 20 mhz t-latch 9 2 test 3 le 10 10 bits 9-17 bits 7-8 bits 4-6 18-bit shift register sync n[1:0] p/s fout test v cc 2 oe p_load fout bits 0-3 ssm-latch oe v cc v cc gnd test v cc v cc gnd fout nc m[3] m[2] m[1] m[0] p_load nc n[1] n[0] m[8] m[7] m[6] m[5] m[4] s_clock s_load v cc_pll v cc_pll nc nc xtal_in 25 26 27 28 29 30 31 32 15 14 13 12 11 10 9 12345678 24 23 22 21 20 19 18 17 16 v cc oe xtal_out s_data MPC92469 fout
idt? / ics? pecl clock synthesizer w/spread spectrum 3 MPC92469rev 4 january 23, 2007 MPC92469 400mhz, low voltage, pecl cloc k synthesizer w/spread spectrum table 1. pin configurations pin i/o default type function xtal_in, xtal_out analog crys tal oscillator interface. fout, fout output lvpecl differential clock output. test output lvcmos test and device diagnosis output. s_load input 0 lvcmos serial configuration control input. this inputs controls the loading of the conf iguration latches with the contents of the shift register. the latches will be transparent when this signal is high, thus the data must be stable on the high-to-low transition. p_load input 1 lvcmos parallel configuration control input. this input controls the loading of the conf iguration latches with the content of the parallel inputs (m and n). t he latches will be transparent when this signal is low, thus the parallel data must be stable on the low-to-high transition of p_load . p_load is state sensitive. s_data input 0 lvcmos serial configuration data input. s_clock input 0 lvcmos serial configuration clock input. m[8:0] input 1 lvcmos parallel configur ation for pll feedback divider (m). m is sampled on the low-to-high transition of p_load . n[1:0] input 1 lvcmos parallel configuration for post-pll divider (n). n is sampled on the low-to-high transition of p_load . oe input 1 lvcmos output enable (active high). the output enable is synchronous to the out put clock to eliminate the possibility of runt pulses on the f out output. oe = l low stops f out in the logic low state (f out = l, fout = h). gnd supply supply ground negative power supply (gnd). v cc supply supply v cc positive power supply for i/o and core. all v cc pins must be connected to the positive power supply for correct operation. v cc_pll supply supply v cc pll positive power supply (analog power supply). table 2. output frequency range and pll post-divider n n output division output frequency range n1 n0 0 0 1 200 ? 400 mhz 0 1 2 100 ? 200 mhz 1 0 4 50 ? 100 mhz 1 1 8 25 ? 50 mhz
MPC92469 400mhz, low voltage, pecl cloc k synthesizer w/spread spectrum idt? / ics? pecl clock synthesizer w/spread spectrum 4 MPC92469rev 4 january 23, 2007 table 3. general specifications symbol characteristics min typ max unit condition v tt output termination voltage v cc ? 2 v mm esd protection (machine model) 200 v hbm esd protection (human body model) 2000 v lu latch-up immunity 200 ma c in input capacitance 4.0 pf inputs ja lqfp 32 thermal resistan ce junction to ambient single layer test board multi-layer test board 67.8 55.9 50.1 47.9 42.1 39.4 c/w c/w c/w c/w c/w c/w 0 lfpm 200 lfpm 500 lfpm 0 lfpm 200 lfpm 500 lfpm jc lqfp 32 thermal resistance junction to case 23.0 26.3 c/w mil-spec 883e method 1012.1 table 4. absolute maximum ratings (1) 1. absolute maximum continuous ratings are those maximum val ues beyond which damage to the device may occur. exposure to these conditions or conditions beyond t hose indicated may adversely affect device reliabi lity. functional operat ion at absolute-maxim um-rated conditions is not implied. symbol characteristics min max unit condition v cc supply voltage ?0.3 3.9 v v in dc input voltage ?0.3 v cc + 0.3 v v out dc output voltage ?0.3 v cc + 0.3 v i in dc input current 20 ma i out dc output current 50 ma t s storage temperature ?65 125 c table 5. dc characteristics (v cc = 3.3 v 5%, t a = 0c to +70c) symbol characteristics min typ max unit condition lvcmos control inputs (p_load , s_load, s_data, s_clock, m[0:8], n[0:1]. oe) v ih input high voltage 2.0 v cc + 0.3 v lvcmos v il input low voltage 0.8 v lvcmos i in input current (1) 1. inputs have pull-down resistors affecting the input current. 200 av in = v cc or gnd differential clock output f out (2) 2. outputs terminated 50 ? to v tt = v cc ? 2 v. v oh output high voltage (3) 3. the MPC92469 test output levels are compatible to the mc12429 output levels. v cc ?1.11 v cc ?0.74 v lvpecl v ol output low voltage (3) v cc ?1.95 v cc ?1.60 v lvpecl test and diagnosis output test v oh output high voltage (3) 2.0 v i oh = ?0.8 ma v ol output low voltage (3) 0.55 v i oh = 0.8 ma supply current i cc_pll maximum pll supply current 8 ma v cc_pll pins i cc maximum supply current 95 ma all v cc pins
idt? / ics? pecl clock synthesizer w/spread spectrum 5 MPC92469rev 4 january 23, 2007 MPC92469 400mhz, low voltage, pecl cloc k synthesizer w/spread spectrum table 6. ac characteristics (v cc = 3.3 v 5%, t a = 0c to +70c) (1) 1. ac characteristics apply for par allel output termination of 50 ? to v tt . symbol characteristics min typ max unit condition f xtal crystal interface frequency range 12 20 mhz f vco vco frequency range (2) 2. the input frequency f xtal and the pll feedback divider m must match the vco frequency range: f vco = f xtal x m 8. 400 800 mhz f max output frequency n = 00 ( 1) n = 01 ( 2) n = 10 ( 4) n = 11 ( 8) 200 100 50 25 400 200 100 50 mhz mhz mhz mhz dc output duty cycle 48 50 52 % t r , t f output rise/fall time 0.05 0.3 ns 20% to 80% f s_clock serial interface programming clock frequency (3) 3. the frequency of s_clock is limited to 10 mhz in serial pr ogramming mode. s_clock can be switched at higher frequencies when used as test clock in test mode 6. see applications information for more details. 10 mhz t p,min minimum pulse width (s_load, p_load )50 ns t s setup time s_data to s_clock s_clock to s_load m, n to p_load 20 20 20 ns ns ns t s hold time s_data to s_clock m, n to p_load 20 20 ns ns t jit(cc) cycle-to-cycle jitter 50 ps n 8 t jit(per) period jitter 50 ps n 8 t lock maximum pll lock time 10 ms ssm fmod spread spectrum modulation frequency 32 khz f xtal = 16 mhz ssm dev spread spectrum modulation deviation ss[3:0] = 0001 ss[3:0] = 1001 0.30 -0.3 0.5 -0.5 % % f out = 300 mhz f xtal = 16 mhz
MPC92469 400mhz, low voltage, pecl cloc k synthesizer w/spread spectrum idt? / ics? pecl clock synthesizer w/spread spectrum 6 MPC92469rev 4 january 23, 2007 programming interface programming the MPC92469 programming the MPC92469 amounts to properly configuring the internal pll dividers to produce the desired synthesized frequency at the output. the output frequency can be represented by this formula: f out = (f xtal 16) x (m) (n) (1) where f xtal is the crystal frequency, m is the pll feedback- divider and n is the pll post-divider. the input frequency and the selection of the feedback divider m is limited by the vco-frequency range. f xtal and m must be configured to match the vco frequency range of 400 to 800 mhz in order to achieve stable pll operation: m min = f vco,min f xtal * 8 and (2) m max = f vco,max f xtal * 8 (3) for instance, the use of a 16 mhz input frequency requires the configuration of the pll feedback divider between m = 200 and m = 400. ta b l e 7 shows the usable vco frequency and m divider range for other example input frequencies. assuming that a 16 mhz input frequency is used, equation 1 reduces to: f out = m n(4) table 7. MPC92469 frequency operating range mm[8:0] vco frequency for a crystal interface frequency of output frequency for f xtal = 16 mhz and for n = 12 14 16 18 20 1 2 4 8 160 010100000 400 170 010101010 425 180 010110100 405 450 190 010111110 427.5 475 200 011001000 400 450 500 200 100 50 25 210 011010010 420 472.5 525 210 105 52.5 26.25 220 011011100 440 495 550 220 110 55 27.50 230 011100110 402.5 460 517.5 575 230 115 57.5 28.75 240 011110000 420 480 540 600 240 120 60 30 250 011111010 437.5 500 562.5 625 250 125 62.5 31.25 260 100000100 455 520 585 650 260 130 65 32.50 270 100001110 405 472.5 540 607.5 675 270 135 67.5 33.75 280 100011000 420 490 560 630 700 280 140 70 35 290 100100010 435 507.5 580 652.5 725 290 145 72.5 36.25 300 100101100 450 525 600 675 750 300 150 75 37.5 310 100110110 465 542.5 620 697.5 775 310 155 77.5 38.75 320 101000000 480 560 640 720 800 320 160 80 40 330 101001010 495 577.5 660 742.5 330 165 82.5 41.25 340 101010100 510 595 680 765 340 170 85 42.5 350 101011110 525 612.5 700 787.5 350 175 87.5 43.75 360 101101000 540 630 720 360 180 90 45 370 101110010 555 647.5 740 370 185 92.5 46.25 380 101111100 570 665 760 380 190 95 47.5 390 110000110 585 682.5 780 390 195 97.5 48.75 400 110010000 600 700 800 400 200 100 50 410 110011010 615 717.5 420 110100100 630 735 430 110101110 645 752.5 440 110111000 660 770 450 111000010 675 787.5 510 111111110 765
idt? / ics? pecl clock synthesizer w/spread spectrum 7 MPC92469rev 4 january 23, 2007 MPC92469 400mhz, low voltage, pecl cloc k synthesizer w/spread spectrum substituting n for the four avail able values for n (1, 2, 4, 8) yields: example frequency calculation for an 16 mhz input frequency if an output frequency of 131 mhz was desired the following steps would be taken to identify the appropriate m and n values. according to ta b l e 8 , 131 mhz falls in the frequency set by an value of 2 so n[1:0] = 01. for n = 2 the output frequency is f out = m 2 and m = f out x 2. therefore m = 2 x 131 = 262, so m[8:0] = 100000110. following this procedure a user can generate any whole frequency between 25 mhz and 400 mhz. note than for n > 2 fractional values of can be realized. the size of the programmable frequency steps (and thus the indicator of the fractional output frequencies achievable) will be equal to: f step = f xtal 16 n(5) applications information using the parallel an d serial interface the m and n counters can be loaded either through a parallel or serial interface. the parallel interface is controlled via the p_load signal such that a low-to-high transition will latch the information present on the m[8:0] and n[1:0] inputs into the m and n counters. when the p_load signal is low the input latches will be transparent and any changes on the m[8:0] and n[1:0] input s will affect the fout output pair. to use the serial port the s_clock signal samples the information on the s_data line and loads it into a 14 bit shift register. note that the p_load signal must be high for the serial load operation to function. the ssm register is loaded with the first four bits, the test register is loaded with the next three bits, the n register with t he next two and the m register with the final eight bits of the data stream on the s_data input. for each register the most significant bit is loaded first (t2, n1 and m8). a pulse on the s_load pin after the shift register is fully loaded will transfer the divide values into the counters. the high-to-low transition on the s_load input will latch the new divide values into the counters. figure 3 illustrates the timing diagram for both a parallel and a serial load of the MPC92469 synthesizer. m[8:0] and n[1:0] are normally specified once at pow er-up through the parallel interface, and then possibly again through the serial interface. this approach allows the application to come up at one frequency and then change or fine-tune the clock as the ability to control the serial interface becomes available. using the test and diagnosis output test the test output provides visibility for one of the several internal nodes as determined by the t[2:0] bits in the serial configuration stream. it is not configurable through the parallel interface. although it is possible to select the node that represents f out , the cmos output is not able to toggle fast enough for higher output frequencies and should only be used for test and diagnosis. the t2, t1 and t0 control bits are preset to ?000' when p_load is low so that the pecl fout outputs are as jitter-free as possible. any active signal on the test output pin will have detrimental affects on the jitter of the pecl output pair . in normal operations, jitter specifications are only guar anteed if the test output is static. the serial configuration port can be used to select one of the alternate functions for this pin. most of the signals available on the test output pin are useful only for performance verification of the MPC92469 itself. however the pll bypass mode may be of interest at the board level for functional debug. when t[2:0] is set to 110 the MPC92469 is placed in pll bypass mode. in this mode the s_clock input is fed directly into the m and n dividers. the n divider drives the f out differential pair and the m counter drives the test output pin. in this mode the s_clock input could be used for low speed board level functional test or debug. bypassing the pll and driving f out directly gives the user more control on the test clocks sent through the clock tree. because the s_clock is a cmos level the input frequency is limited to 200 mhz. this means the fastest the f out pin can be toggled via the s_clock is 100 mhz as the divide ratio of the post-pll divider is 2 (if n = 1). note that the m counter output on the test output wi ll not be a 50% duty cycle. table 8. output frequency range for f xtal = 16 mhz n f out f out range f out step 1 0 value 0 0 1 m 200 ? 400 mhz 1 mhz 0 1 2 m 2 100 ? 200 mhz 500 khz 1 0 4 m 4 50 ? 100 mhz 250 khz 1 1 8 m 8 25 ? 50 mhz 125 khz table 9. test and debug configuration for test t[2:0] test output t2 t1 t0 0 0 0 18-bit shift register out (1) 1. clocked out at the rate of s_clock. 0 0 1 logic 1 0 1 0 f xtal 16 0 1 1 m-counter out 1 0 0 fout 1 0 1 logic 0 1 1 0 m-counter out in pll-bypass mode 1 1 1 fout 4 table 10. debug configuration for pll bypass (1) 1. t[2:0] = 110. ac specifications do not apply in pll bypass mode. output configuration f out s_clock n test m-counter out (2) 2. clocked out at the rate of s_clock (4 ? n)
MPC92469 400mhz, low voltage, pecl cloc k synthesizer w/spread spectrum idt? / ics? pecl clock synthesizer w/spread spectrum 8 MPC92469rev 4 january 23, 2007 figure 3. serial interface timing diagram figure 4. down spread % across vco range with 16 mhz reference figure 5. center spread % across vco range with 16 mhz reference s_clock s_data s_load m[8:0] n[1:0] p_load t2 t1 t0 n1 n0 m8 m7 m6 m5 m4 m3 m2 m1 m0 m, n first bit last bit ss1 ss2 ss0 ss3
idt? / ics? pecl clock synthesizer w/spread spectrum 9 MPC92469rev 4 january 23, 2007 MPC92469 400mhz, low voltage, pecl cloc k synthesizer w/spread spectrum spread spectrum modulation the MPC92469 offers the option of a spread spectrum (ssm) output clock and is controll ed by four bits in the serial load bit stream. these four bits configure the ssm to be enabled, the type of spread and the amount of spread modulation to be selected. ta b l e 11 shows the definition of these four bits. these spread control bits are located at the beginning of the serial data stream and are labeled ss3, ss2, ss1 and ss0. the initial state of these four bits (ss3:ss0) is 0000 which places the MPC92469 in the configuration of ssm being off. any parallel load operation will also result in the spread spectrum modulation programming being reset to the value 0000 which likewise turns spread spectrum modulation off. the MPC92469 offers down-spread or center spread. figure 4 and figure 5 show the amount of spread based upon both the vco frequency and the spread spectrum control bit pattern. figure 4 is for down-spread with 0% spread being at the top of the fi gure. figure 5 is for center- spread with 0% spread in the mi ddle of the figure. increasing values of ss2:ss0 increase the amount of spread and ss3 is used to configure either center-spread (ss3=0) or down- spread (ss3=1). note, for both tables, the horizontal axis is the vco frequency which ranges from 400mhz to 800mhz. the vco frequency is 2x the output frequency which corresponds to an output frequency range of 200mhz to 400mhz for the output divider of n=1. table 11. ssm operation power supply filtering the MPC92469 is a mixed analog/digital product. its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. random noise on the v cc_pll pin impacts the device characteristics. the MPC92469 provides separate power supplies for the digital circuitry (v cc ) and the internal pll (v cc_pll ) of the device. the purpose of this design technique is to try and isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. in a controlled environment such as an evaluation board, this level of isolation is sufficient. however, in a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. the simplest form of isolation is a power supply filter on the v cc_pll pin for the MPC92469. figure 6 illustrates a typical power supply filter scheme. the MPC92469 is most susceptible to noise with spectral content in the 1 khz to 1 mhz range. therefore, the filter should be designed to target this range. the key parameter that needs to be met in the final filter design is the dc voltage drop that will be seen between the v cc supply and the v cc_pll pin of the MPC92469. from the data sheet, the v cc_pll current (the current sourced through the v cc_pll pin) is maximum 8 ma, assuming that a minimum of 3.0 v must be maintained on the v cc_pll pin. the resistor shown in figure 6 must have a resistance of 10-15 ? to meet the voltage drop criteria. the rc filter pictured will provide a broadband filter with approximately 100:1 attenuation for noise whose spectral content is above 20 khz. as th e noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. the parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the pll. figure 6. v cc_pll power supply filter additional noise suppression may be achieved with the use of a ferrite chip bead. the ferrite chip bead offers a high value of rf impedance while maintaining a very low dc resistance. ferrite beads are available from 15 ? to over 1k ? rf impedance (measured @ 100 mhz), but would have dc resistance values of less than 1 ? . max current ratings range from a few hundred ma to over 1 a. the selected bead should have a max current rating well in excess of the actual circuit requirements preventing saturation of the ferrite material. the ferrite chip bead is placed in series with a low value resistor as shown in figure 7. capacitor values should be staggered in value by a factor of 5 to 10. proper curcuit modeling should be performed to optimize circuit components in specific user applications. figure 7. v cc_pll power supply filter using a ferrite bead ss bit pattern operation ss3 ss2 ss1 ss0 mode 0000 off 0 0 0 1 ? ? ? 0 1 1 1 center-spread (increasing amount) 1000 off 1 0 0 1 ? ? ? 1 1 1 1 down-spread (increasing amount) v cc_pll v cc MPC92469 c 1 , c 2 = 0.01...0.1 f v cc c f = 22 f r f = 10-15 ? c 2 c 1 0.0047 -0.022 f 10 -25 f 0.047 - 0.1 f pins 4 & 5 vcc_pll 3.3v bulk board capacitance 1 -2 ohms 120 ? 600 ohm ferrite bead 3.3v+-5% MPC92469
MPC92469 400mhz, low voltage, pecl cloc k synthesizer w/spread spectrum idt? / ics? pecl clock synthesizer w/spread spectrum 10 MPC92469rev 4 january 23, 2007 using the on-board crystal oscillator the MPC92469 features a fully integrated pierce oscillator to minimize system implement ation costs. the MPC92469 may be operated with a 12 mhz to 20 mhz crystal and without additional components. reco mmended operation for the crystal should be of a parallel resonant type and a load specification of c l = 18 pf. see table 12 for complete crystal specifications. if more precise frequency contro l is desired, the addition of capacitors from each of the xt al_in and xtal_out pins to ground may be used to trim the frequency as shown in figure 8. the crystal and optional trim capacitors should be located as close to the MPC92469 xtal_in and xtal_out pins as possible to avoid any board level parasitic. figure 8. crystal oscillat or with trim capacitor table 12. recommended crystal specifications parameter value crystal cut fundamental at cut resonance parrallel resonance shunt capacitance (c l ) 5?7 pf load capacitance (c o ) 18 pf equivalent series resistance (esr) 20 to 50 ? table 12. recommended crystal specifications MPC92469 xt al_in xtal_out 12 - 20 mhz 5 pf 5 pf
idt? / ics? pecl clock synthesizer w/spread spectrum 11 MPC92469rev 4 january 23, 2007 MPC92469 400mhz, low voltage, pecl cloc k synthesizer w/spread spectrum figure 9. package drawing for 32 lead lqfp table 13. package dimensions for 32lead lqfp n o i t a i r a v c e d e j s r e t e m i l l i m n i s n o i s n e m i d l l a l o b m y s a b b m u m i n i mla n i m o nmu m i x a m n 2 3 a - -- -0 6 . 1 1 a 5 0 . 0- -5 1 . 0 2 a 5 3 . 10 4 . 15 4 . 1 b 0 3 . 07 3 . 05 4 . 0 c 9 0 . 0- -0 2 . 0 d c i s a b 0 0 . 9 1 d c i s a b 0 0 . 7 2 d . f e r 0 6 . 5 e c i s a b 0 0 . 9 1 e c i s a b 0 0 . 7 2 e . f e r 0 6 . 5 e c i s a b 0 8 . 0 l 5 4 . 00 6 . 05 7 . 0 0 ? - - 7 ? c c c - -- -0 1 . 0 nominal maximum
MPC92469 400mhz, low voltage, pecl cloc k synthesizer w/spread spectrum ? 2006 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited 321 kingston road leatherhead, surrey kt22 7tu england +44 (0) 1372 363 339 fax: +44 (0) 1372 378851 for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support netcom@idt.com 480-763-2056 innovate with idt and accelerate your future netw orks. contact: www.idt.com

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